1. Field of the Invention
The present invention relates to a method of manufacturing a memory, and more particularly to a method of manufacturing a dynamic random access memory (DRAM).
2. Description of Related Art
With the development of powerful microprocessors, the software is more capable of programming and calculating an increasing amount of data. Therefore, the fabrication of memories is essential in the semiconductor industry. A dynamic random access memory (DRAM) is a volatile memory (VM) and is formed by a plurality of memory cells. Each memory cell herein is mainly composed of a transistor and a capacitor, and all memory cells are electrically connected to one another through word lines (WLs) and bit lines (BLs). In addition, said capacitor is generally called a storage node (SN).
Due to an increase in integrity of devices, the DRAM devices are miniaturized to meet market demands. Thus, the DRAM having a capacitor-over-bit-line (COB) structure has been developed. In general, the COB-structured DRAM is fabricated by forming a shallow trench isolation (STI) structure in a substrate to define an active area of the memory cell and then forming the transistor in the active area. After that, a dielectric layer isolates the transistor, and a bit line contact (BLC) opening is then formed in the dielectric layer. Thereafter, the BLC connecting the transistor is formed in the BLC opening and the BL connecting the BLC is formed on the dielectric layer. Afterwards, another dielectric layer is formed on the BL, and a storage node contact (SNC) opening is formed in said two dielectric layers. Next, an SNC is formed in the SNC opening and an SN is formed on the second dielectric layer.
However, during the formation of said DRAM, the lattice of the material of a barrier layer below the BL is usually altered due to excessive manufacturing temperature, and thereby the material is connected to the SNC by passing through a spacer of the SNC, resulting in a short circuit between the BL and the SNC.